Due to the high degree of complexity and high density of modern integrated circuitry, manufacturers of integrated circuits (ICs) typically use highly-sophisticated Automated Test Equipment (ATE) to test integrated circuits, to ensure that they perform as designed (e.g., to specification). Some high-volume integrated circuit users also utilize ATEs to verify the function of integrated circuits (usually on a sampled basis). Without using an ATE, or the like, it would be virtually impossible to achieve high confidence levels with respect to integrated circuit functionality and reliability.
Automated test equipment (ATE) provides the ability to generate test signal sequences on a large number of pins of an integrated circuit device under test (DUT), in some cases simultaneously. Unlike ordinary digital equipment, however, ATE is capable of tightly controlling signal timing and voltage characteristics to within a small margin of error. Timing relationships between signals, rise times, fall times, etc., provided by the ATE are all well defined at the pins of the DUT. Additionally, the ATE is capable of making accurate measurements of voltage levels and timing of signals emanating from the DUT in response to the signal sequences (e.g., test vectors). These capabilities are provided at very high speed under the control of a pre-defined test program. Further, most automated test equipment include programmable voltage sources for applying to the DUT. These voltages are sometimes referred to as "bias" voltages or "bias" signals, and are generally used to supply power to the DUT via its power and ground pins.
For analog integrated circuit functions, some automated test equipment includes high-speed waveform signal generators, the outputs of which can be applied to analog function pins of the DUT. Similarly, such analog capability usually includes some sort of high-speed voltage sampling capability. Sometimes, these analog capabilities are applied to digital functions as a part of a test in order to ensure compliance of a DUT with pre-specified signal threshold levels, hysteresis, etc.
FIG. 1a is a block diagram of a typical automated tester (ATE) for integrated circuits. The ATE 100 comprises a test sequencer 130 which operates under the control of a stored test program 140 to control programmable pin drivers/monitors 110 and programmable power supplies (voltage sources) 120. The programmable power supplies 120 are controlled by the program 140 to generate suitable power supply voltages to be applied to a DUT 170. The specific power supply voltages are selected to suit specific test requirements. For example, it might be desirable to test a DUT 170, e.g., a CMOS (Complementary Metal Oxide Semiconductor) IC, at minimum, nominal, and maximum power supply voltages to ensure compliance of the DUT with specified performance parameters at those voltages. Accordingly, three sets of test signal sequences would be generated under control of the program 140, each sequence altering the power supply voltages to reflect minimum, nominal, or maximum rated power supply specifications for the DUT 170. The programmable pin drivers/monitors 110 would be controlled by the program 140 (via the test sequencer 130) to generate high-speed digital test signals (vectors) to be applied to the DUT 170 and to monitor and measure various parameters of specific signals generated by the DUT 170 in response to the test signals. (ATE pin drivers can usually also be set to a high-impedance state, essentially leaving the associated DUT pin "unconnected").
The output signals (and monitor inputs) of the programmable pin drivers/monitors 110 and the outputs of the programmable power supplies 120 are provided to the DUT 170 via a DUT interface board 160 connected to a test interface connector 150 on the ATE 100. The signals and supply voltages are routed through the test interface connector 150 via contacts or connections on the DUT board 160 to pins of a DUT socket or connector 165 mounted to the DUT board 160. The DUT 170 "plugs into" the test interface connector 165. (The term "plugs into" is used loosely here, since the DUT connector 165 is usually a specialized test connector, such as a "zero-insertion-force" connector, designed to minimize the mechanical stress placed upon the pins or contacts of the DUT 170).
Referring to FIG. 1b, the DUT board 160, is essentially a test fixture designed to adapt the DUT 170 to the test interface connector 150 of the ATE 100. Typically, the DUT board 160 is a very thick, rigid printed circuit board with contact pads on a bottom side thereof (not shown) to make contact with spring-loaded contactors in the test interface connector 150. Often, the DUT board is clamped to the test interface connector 150 via a camlocking arrangement (not shown). Signal traces 162 (a representative few shown) on the top of the DUT board connect the contact pads (on the bottom of the DUT board) to the DUT connector 165.
Although most modern integrated circuits are assembled into one of a relatively small number of different package types, there is little standardization of pinouts on these packages, particularly with respect to power supply connections. Most PLCC (plastic leaded chip carrier), PQFP (plastic quad flat pack), and PGA devices, particularly those with large numbers of "pins" (e.g., 100 or more), will have several "pins" dedicated to each of the power supply voltages. Unfortunately (e.g., for testing purposes), the selection of these power supply pins is usually different for different ICs, despite the use of identical package types. Consequently, it has been necessary to provide a different DUT board (e.g., 160) for each different IC. Each different DUT board will have power supply signals (bias signals) routed to different pins of the DUT connector, as required by the specific IC to be tested.
There is considerably greater flexibility with respect to the programmable pin drivers/monitors (e.g., 120) since their operation is governed by a test program. A specified test signal sequence can be routed to any connected pin (other than the power supply pins, of course) simply by specifying the appropriate pin driver/monitor in the test program (e.g., 140).
DUT boards must generally be built to relatively tight mechanical tolerances and must use relatively expensive, high-quality materials to ensure good contact between the various connections, and to ensure long service life. As a result, a DUT board can sometimes cost as much as $4000.00. This is particularly troublesome to ASIC (Application Specific Integrated Circuit) vendors, for whom practically every customer has a different IC design. As a result, each IC for each customer must have a custom-built DUT board. These DUT boards add expense to the cost of developing the IC, represent a significant storage problem (these boards are relatively large, and must be kept on hand for subsequent production runs of the customers ICs) and can potentially delay delivery of initial quantities of ICs to the customer (due to the fabrication time required for the DUT board).
Evidently, it would be highly advantageous to provide some means of eliminating or minimizing the delay, storage requirements, and expense associated with the design and fabrication of DUT boards.